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Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
CMA8864-04 (3 DIMM)
FEATURES
l l
I2C, Mixed Voltage clock Synthesizer with Buffer for PENTIUMTM & II CPU/PCI system (CK3D)
l l l l l
Supports Pentium and Pentium II CPUs. Two (2) copies of CPUCLK clock powered with VDDL2, two (2) copies of CPUCLK powered with VDD3.. Twelve (12) SDRAM clocks powered by VDD3. Seven (7) copies of PCI clock (1/2 CPU clock or asynchronous 2/5 CPU clock). IOAPIC clock @14.318MHz driven by VDDL1. 24/48 MHz outputs (3.3V TTL) Two Ref. Clock @ 14.318MHz (3.3V TTL).
l l
60mA buffer switching current @3.3V. Optional common or mixed power supply mode VDD1, 2, 3 = VDDL2, 1 = 3.3V VDD1, 2, 3 = 3.3V; VDDL2, 1 = 2.5V l < 250ps skew between CPU/SDRAM buffers. l <500ps skew between PCI buffers. l Power management controlled by CPU_STOP#, PCI_STOP#. l I2C Serial configuration interface. l 48 pins SSOP package.
PIN CONFIGURATIONS
VDD1 *REF0 / CPU3.3#_2.5 GND XTAL_IN XTAL_OUT VDD2 *PCICLK_F / FS1 *PCICLK1 / FS2 GND PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDD2 PCICLK6 / PCI_STOP# GND SDRAM12 SDRAM11 VDD3 SDRAM10 SDRAM9 GND SDATA I2C SDCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1 / CPU_STOP# GND CPUCLK1 CPUCLK2 VDDL2 CPUCLK3 CPUCLK4 GND SDRAM1 SDRAM2 VDD3 SDRAM3 SDRAM4 GND SDRAM5 SDRAM6 VDD3 SDRAM7 SDRAM8 GND 48MHz / FS0* 24MHz / MODE*
2.5V / 3.3V I/O PINS
*Internal pull-up resistor 240 [ to 3.3V on indicated pins.
POWER GROUPS
VDD1=REF, XTAL_IN, XTAL_OUT, PLL CORE VDD3=SDRAM, 24/48MHz, CPUCLK3- 4 VDDL2=CPUCLK1-2 VDD2=PCICLK VDDL1=IOAPIC
CMEI
1
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
PIN DESCRIPTION
NAME
VDD1 REF0 / CPU3.3#_2.5 GND XTAL_IN XTAL_OUT VDD2 PCICLK_F / FS1 PCICLK1 / FS2 PCICLK2-5 PCICLK6 / PCI_STOP# SDRAM12-1
TYPE
P I/O G I O P I/O I/O O I/O O
NO.
1 2 3, 9, 16, 22, 27, 33, 39, 45 4 5 6, 14 7 8 10, 11, 12, 13 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 19, 30, 36 20, 21, 28, 29, 31, 32, 34, 35,37, 38 23 24 25
DESCRIPTION
Analog 3.3V power supply for PLL core, REF, XTAL_IN/_OUT. 14.318MHz clock output. / Indicates VDDL2 power supply, 0=3.3V CPU, 1=2.5V CPU. Ground. Crystal input. Crystal output. 3.3V I/O power supply for PCICLK. PCI clock output free-running, TTL compatible 3.3V. / Frequency select pin, latched input, internal pull-High. PCI clock output TTL compatible 3.3V. / Frequency select pin, latched input, internal pull-High. PCI clock output TTL compatible 3.3V. PCI clock output TTL compatible 3.3V. / halts PCICLK at logic 0 level when input low, MODE=0 (Mobil mode) SDRAM clock output.
VDD3 SDRAM10:1
P O
3.3V I/O power supply for SDRAM, 24/48MHz. SDRAM clock outputs powered by VDD3. Data input pin for I2C bus. Clock input pin for I2C bus. 24MHz clock output 3.3V. MODE=1 Pin 15 = PCICLK6 Pin 46 = REF1 MODE=0 Pin 15 = CPI_STOP# Pin 46 = CPU_STOP# 48MHz clock output 3.3V. / Frequency select pin, latched input, internal pull-High. CPU and Host clock output 3.3V output, powered by VDD3. CPU and Host clock output 3.3V output, powered by VDD3. 2.5V/3.3V I/O power supply. CPU and Host clock output 2.5V/3.3V output, powered by VDDL2. CPU and Host clock output 2.5V/3.3V output, powered by VDDL2. 14.318MHz clock output. / halts CPUCLK at logic 0 level when input low, MODE=0 (Mobil mode) 14.318MHz clock output 2.5V/3.3V, powered by VDDL1. 2.5V/3.3V I/O power supply.
SDATA SDCLK 24MHz / MODE 48MHz / FS0 CPUCLK4 CPUCLK3 VDDL2 CPUCLK2 CPUCLK1 REF1 / CPU_STOP# IOAPIC VDDL1
I I I/O
I/O O O P O O I/O I/O P
26 40 41 42 43 44 46 47 48
CMEI
2
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
CPU CLOCK FREQUENCY TABLE (in MHz)
SEL2 SEL1 SEL0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CPU, SDRAM 66.8 60 75 83.3 68.5 83.3 75 50 PCI 33.4 (1/2 CPU) 30 (1/2 CPU) 37.5 (1/2 CPU) 33.3 (2/5 CPU) 34.25 (1/2 CPU) 41.65 (1/2 CPU) 30 (2/5 CPU) 25 (1/2 CPU)
I2C SERIAL CONTROL I2C Specification
Address assignment Transfer type Transfer rate Data byte format Address format General call 7 bit Slaver / Receiver 100kbits/s (standard mode) 8 bits A6 A5 A4 A3 A2 A1 1 1 0 1 0 0 No respond
A0 R/Ws +8 bits dummy +8 bits dummy 1 0 Command Code Command Code
SERIAL CONTROL REGISTERS
A) The serial bits will be read in the following order : Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N Bits 7, 6, 5, 4, 3, 2, 1, 0
B) The PIN# column lists the affected pin number where application. The values in the @Pup column gives the state at true power up. Registers are set to the values shown only on the true power up.
CMEI
3
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
Byte 0 : Function and Frequency Select Register (1=enable, 0=disable)
Bit
7
PIN#
--
@Pup
0
Description
Must be 0 for normal operation. 0 -- O frequency modulation. 1.5% 1 -- O frequency modulation. 0.5% Bit6 Bit5 Bit4 CPU, SDRAM PCI 33.4 (1/2 CPU) 66.8 1 1 1 30 (1/2 CPU) 60 0 1 1 37.5 (1/2 CPU) 75 1 0 1 33.3 (2/5 CPU) 83.3 0 0 1 34.5 (1/2 CPU) 68.5 1 1 0 41.65 (1/2 CPU) 83.3 0 1 0 30 (2/5 CPU) 75 1 0 0 25 (1/2 CPU) 50 0 0 0 0 -- Frequency is selected by hardware select, latched inputs. 1 -- Frequency is selected by Bit 6 : 4. Must be 0 for normal operation. 0 -- Frequency modulation center spread type. 1 -- Frequency modulation down spread type. 0 -- Normal. 1 -- Frequency modulation enabled type. 0 -- Normal. 1 -- Tristate all outputs.
6 5 4
----
0 0 0
3 2
---
0 0
1 0
---
0 0
Byte 1 : CPU Active/Inactive Register (1=enable, 0=disable)
Bit 7 6 5 4 3 2 1 0 PIN# 26 25 --40 41 43 44 @Pup 1 1 X X 1 1 1 1 Description 48MHz (Active/Inactive) 24MHz (Active/Inactive) Reserved Reserved CPUCLK4 (Active/Inactive) CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive)
Byte 2 : PCI Active/Inactive Register (1=enable, 0=disable)
Bit 7 6 5 4 3 2 1 0 PIN# -7 15 13 12 11 10 8 @Pup X 1 1 1 1 1 1 1 Description Reserved PCICLK_F (Active/Inactive) PCICLK6 (Active/Inactive) PCICLK5 (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive)
CMEI
4
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
Byte 3 : SDRAM Active/Inactive Register (1=enable, 0=disable)
Bit 7 6 5 4 3 2 1 0 PIN# 28 29 31 32 34 35 37 38 @Pup 1 1 1 1 1 1 1 1 Description SDRAM8 (Active/Inactive) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive)
Byte 4 : Additional SDRAM Active/Inactive Register (1=enable, 0=disable)
Bit 7 6 5 4 3 2 1 0 PIN# ----17 18 20 21 @Pup X X X X 1 1 1 1 Description Reserved Reserved Reserved Reserved SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive)
Byte 5 : Peripheral Active/Inactive Register (1=enable, 0=disable)
Bit 7 6 5 4 3 2 1 0 PIN# ---47 --46 2 @Pup X X X 1 X X 1 1 Description Reserved Reserved Reserved IOAPIC (Active/Inactive) Reserved Reserved REF1 (Active/Inactive) REF0(Active/Inactive)
Byte 6 : Reserved Optional Register for Future Requirements
Bit 7 6 5 4 3 2 1 0 PIN# --------@Pup X X X X X X X X Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
CMEI
5
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
BUFFER SPECIFICATION
Buffer Name CPU IOAPIC 24/48MHz, REF1, 2 ,REF0, SDRAM PCI Vcc Range (V) 2.375 - 2.9 2.375 - 2.9 3.315 - 3.465 3.315 - 3.465 3.315 - 3.465 Impedance ( [ ) 15 - 45 10 - 30 20 -60 10 - 24 12 - 55 Buffer Type 1 2 3 4 5
Type 1 : CPU clock buffer Operating Characteristics Symbol Parameter Condition Min. Max.
Iohmin Iohmax Iolmin Iolmax trh tfh Pull-up Current Pull-up Current Pull-down Current Pull-down Current 2.5V Type 1 output Rise Edge Rate 2.5V Type 1 output Fall Edge Rate Vout=1.0V Vout=2.6V Vout=1.2V Vout=0.3V 2.5V @2.0V-0.4V 10pF load 2.5V @2.0V-0.4V 20pF load -27 -27 27 1/1 1/1 27 4/1 4/1
Units
mA mA mA mA V/ns V/ns
Type 2 : IOAPIC (2.5V) clock buffer Operating Characteristics Symbol Parameter Condition Min. Max. Units
Iohmin Iohmax Iolmin Iolmax trh tfh Pull-up Current Pull-up Current Pull-down Current Pull-down Current 2.5V Type 2 output Rise Edge Rate 2.5V Type 2 output Fall Edge Rate Vout=1.4V Vout=2.7V Vout=1.0V Vout=0.2V 2.5V @0.4V-2.0V 10pF load 2.5V @2.0V-0.4V 20pF load -36 -29 36 1/1 1/1 28 4/1 4/1 mA mA mA mA V/ns V/ns
Type 3 : FD, USB, REF1, 2 (3.3V) clock buffer Operating Characteristics Symbol Parameter Condition Min. Max. Units
Iohmin Iohmax Iolmin Iolmax trh tfh Pull-up Current Pull-up Current Pull-down Current Pull-down Current 3.3V Type 3 output Rise Edge Rate 3.3V Type 3 output Fall Edge Rate Vout=1.0V Vout=3.315V Vout=1.95V Vout=0.4V 3.3V @0.4V-2.4V 10pF load 3.3V @2.4V-0.4V 20pF load -29 -23 29 0.5 0.5 27 2.0 2.0 mA mA mA mA V/ns V/ns
CMEI
6
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
Type 4 : REF0, SDRAM (3.3V) clock buffer Operating Characteristics Symbol Parameter Condition Min. Max. Units
Iohmin Iohmax Iolmin Iolmax trh tfh Pull-up Current Pull-up Current Pull-down Current Pull-down Current 3.3V Type 4 output Rise Edge Rate 3.3V Type 4 output Fall Edge Rate Vout=2.0V Vout=3.315V Vout=1.0V Vout=0.4V 3.3V @0.4V-2.4V 20pF load 3.3V @2.4V-0.4V 30pF load -54 -46 54 1.5 1.5 53 4/1 4/1 mA mA mA mA V/ns V/ns
Type 5 : PCI clock buffer Operating Characteristics Symbol Parameter Condition Min. Max.
Iohmin Iohmax Iolmin Iolmax trh tfh Pull-up Current Pull-up Current Pull-down Current Pull-down Current 3.3V Type 5 output Rise Edge Rate 3.3V Type 5 output Fall Edge Rate Vout=1.0V Vout=3.315V Vout=1.95V Vout=0.4V 3.3V @0.4V-2.4V 20pF load 3.3V @2.4V-0.4V 30pF load -33 -33 30 1/1 1/1 38 4/1 4/1
Units
mA mA mA mA V/ns V/ns
AC / DC SPECIFICATION ABSOLUTE MAXIMUM RATINGS
RATING
Power Supply Voltage
VALUE
VDD=3.3V O 5% VDD3=3.3V O 5% VDDL=2.5V+16%, -5% Applied Input Voltage (VSS) -0.3V Ambient Temperature 55 to 125 J Storage Temperature -65 to 150 J Maximum Power pplySu 7V NOTICE : This device contains circuitry to protect the inputs against damage due to high static voltage or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range :
VSS<(Vin or Vout)Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD)
CMEI
7
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
DC CHARACTERISTICS
SYMBOL Idd Vil Vih Iil Voh2 Vol2 Voh3 Vol3 Vpoh Vpol Ioz Isc PARAMETER Dynamic Supply Current Input Low Voltage Input High Voltage Input Leakage Current 2.5V Output High Voltage 2.5V Output Low Voltage 3.3V Output High Voltage 3.3V Output Low Voltage PCI bus Output High Voltage PCI bus Output High Voltage Tristate Leakage Current Short Circuit Current MIN. MAX. UNIT TBD mA VSS-0.3 0.8 VDC 2.0 VDD-0.3 VDC -5 +5 uA 2.0 V 0.4 V 2.4 V 0.4 V 2.4 V 0.55 V 10 uA 25 mA CONDITION CPU=66.6MHz, PCI=33.3MHz VDD=3.3V O 5% 0AC CHARACTERISTICS
SYMBOL PARAMETER THrise, THfall Host clock Rise and Fall Time THCP Host Clock Period THCH Host Clock High Time THCL Host Clock Low Time Duty Cycle Duty cycle THSKW Buffer out Skew All Host CLK TJAB Jitter absolute, Host clock TSTB Host/PCI clock stabilization from power-up Toff Host to PIC Offset THSSKW Host to SDRAM skew TPCP PCI clock period TPCH PCI clock High Time TPCL PCI clock Low Time TPSKW Buffer out skew all PCICLK Iol Switching Current Low Ioh Switching Current High MIN. 0.4 15/16.7 5.2/6.0 5.0/5.8 45 1.0 30/33.3 12/13.3 12/13.3 TBD TBD Typ. MAX. UNIT CONDITION 1.6 ns 20pf load/CPU and PCI outputs ns Measured at 1.25V, 66/60MHz ns Measured at 2.0V, 66/60MHz ns Measured at 0.4V, 66/60MHz 50 55 % Refer to Notes below 250 ps Refer to Notes below 250 ps Refer to Notes below 3 ms Refer to Notes below, VDDL=3.3V 4.0 ns Refer to Notes below 250 ps Refer to Notes below ns Measured at 1.5V, 66/60MHz ns Measured at 2.4, 66/60MHz ns Measured at 0.4, 66/60MHz 500 ps Refer to Notes below 60 TBD mA Vol=1.5V 60 TBD mA Voh=1.5V
Notes : Clock period, Jitter, Offset and skew are measured on the rising edge clocks at 1.25V for the 2.5V
clocks and 1.5V for the 3.3V clocks.
CMEI
8
CMA8864-04
Ver. 1.2
6F, No. 100, Sec. 4, Civil Boulevard, Taipei, Taiwan TEL: (02)8773-1100 FAX: 886-2-8773-2211 WWW : http://www.cmedia.com.tw
BLOCK DIAGRAM
REF OSC
VDDL1 IOAPIC VDDL2 CPUCLK1, 2 2 VDD3 2 FS0, 1, 2 3 Delay O 2 O 2.5 O 3 VDD2 7 CPUCLK3, 4
XTAL_IN XTAL_OUT
REF0 / CPU3.3#_2.5 REF1 / CPU_STOP#
PLL1
12 SDRAM1-12 PCICLK_F / FS1 PCICLK1 / FS2 PCICLK2-5 PCICLK6 / PCI_STOP#
SDATA SDCLK
Logic Control
48MHZ / FS0
PLL2
24MHZ / MODE
PACKAGE DIMENSION
48 PIN SSOP
0.61 1.02
7.42 7.59 0.20 0.41
10.16 10.41
0.203 0.343
0.25 0.41
15.75 16.00 2.41 2.79 0.635 TYP.
Unit: mm
CMEI
9
CMA8864-04

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